aFPGA: BeMicro SDK #2

BeMicro SDK, Part 2

The first article describes the installation and the setup required for using the evaluation board with Linux (Debian/Ubuntu). This article will show how to run the a pre-compiled Linux system in the FPGA.

Getting the pre-compiled components

The „Linux on a BeMicro SDK“ site in the Altera wiki hosts the download of the pre-compiled package and some information about this package. The direct download of the package is available here. After downloading the archive unpack it:

$ tar xfz BeMicroSDK_MMU.tgz

An alternative way (with packages for more boards) to get it is by cloning a git repository:

git clone git://

In this repository the content of the download package is under BeMicroSDK/BeMicroSDK_MMU/

Preparing a shell environment

In order to use the Altera tools some preparation in the shell must be made. Include the tools directory into the PATH and add a directory containing libraries needed by the tools to the LD_LIBRARY_PATH  (this settings are tested with version 13.1 of the Altera tools):

$ export PATH=$PATH_TO_ALTERA_INSTALL/quartus/bin:$PATH
$ export PATH=$PATH_TO_ALTERA_INSTALL/nios2eds/bin:$PATH
$ export PATH=$PATH_TO_ALTERA_INSTALL/nios2eds/bin/gnu/H-i686-pc-linux-gnu/bin:$PATH

For later use of this changes put it into the configuration of the shell or a separate script that can be called before starting work.

Setting up the FPGA

At first the FPGA has to be loaded with the configuration file. This file is an so called SRAM object file (*.sof). For such file containing a Nios2 system exists a special FPGA configuration tool. Change into the package directory and configure the FPGA:

$ cd BeMicroSDK_MMU/
$ nios2-configure-sof
Searching for SOF file:
in .

Info: *******************************************************************
Info: Running Quartus II 32-bit Programmer
Info: Command: quartus_pgm --no_banner --mode=jtag -o p;./BeMicroSDK.sof
Info (213045): Using programming cable "USB-Blaster [6-1]"
Info (213011): Using programming file ./BeMicroSDK.sof with checksum 0x00AF7517 for device EP4CE22F17@1
Info (209060): Started Programmer operation at Thu Jul  3 17:44:03 2014
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F30DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Thu Jul  3 17:44:04 2014
Info: Quartus II 32-bit Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 141 megabytes
    Info: Processing ended: Thu Jul  3 17:44:04 2014
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:01

The nios2-configure-sof command (found in the path added above in the PATH environment variable) will pick the (only one) sof-file in the directory, choose the (single available) programmer (give the right one by a parameter if several are available) and configure the FPGA. Now the FPGA is configured with the Nios2 system and it’s possible to

Download the software into the FPGA

The software part of the package contains the Linux kernel that is bundled with an inital ram file system (initramfs). This can be downloaded by another special tool nios2-download. The second command (nios2-terminal) will start a new (JTAG-)terminal immediately after finishing the download. This allows to read all the messages from the booting Linux kernel:

$ nios2-download -g zImage.initramfs.gz ; nios2-terminal
Using cable "USB-Blaster [6-1]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
Downloaded 4921KB in 128.1s (38.4KB/s)
Verified OK                         
Starting processor at address 0xD1000000
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [6-1]", device 1, instance 0

nios2-terminal: Warning: The JTAG cable you are using is not supported for Nios
nios2-terminal: II systems.  You may experience intermittent JTAG communication
nios2-terminal: failures with this cable.  Please use a USB Blaster revision B
nios2-terminal: cable or another supported cable.  Please refer to the file
nios2-terminal: errata.txt included in the Nios II development kit documents
nios2-terminal: directory for more information.

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

Uncompressing Linux... Ok, booting the kernel.
Linux version 2.6.35-00743-ge3b9b64-dirtyWe have 81920 pages of RAM
Memory available: 58572k/6389k RAM, 0k/0k ROM (1988k kernel code, 4400k data)
Hierarchical RCU implementation.
    RCU-based detection of stalled CPUs is disabled.
    Verbose stalled-CPUs detection is disabled.
Calibrating delay loop... 49.25 BogoMIPS (lpj=246272)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
init_BSP(): registering device resources
bio: create slab <bio-0> at 0
Switching to clocksource timer
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
msgmni has been set to 114
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
ttyJ0 at MMIO 0x8805000 (irq = 5) is a Altera JTAG UART
console [ttyJ0] enabled, bootconsole disabled
console [ttyJ0] enabled, bootconsole disabled
mii_id : 0
Altera TSE MII Bus: probed
Found PHY with ID=0x20005c90 at address=0x1
Altera Triple Speed MAC IP Driver(v8.0) developed by SLS,August-2008
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
mmc_spi spi2.0: ASSUMING SPI bus stays unshared!
mmc_spi spi2.0: ASSUMING 3.2-3.4 V slot power
mmc_spi spi2.0: SD/MMC host mmc0, no DMA, no WP, no poweroff
TCP cubic registered
NET: Registered protocol family 17
mmc_spi spi2.0: can't change chip-select polarity
Freeing unused kernel memory: 3852k freed (0xd01f3000 - 0xd05b5000)
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SDHC card on SPI
mmcblk0: mmc0:0000 00000 7.35 GiB
 mmcblk0: p1
Welcome to
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    _   _| |  | | _ ____  _   _  _  _
   | | | | |  | || |  _ \| | | |\ \/ /
   | |_| | |__| || | | | | |_| |/    \
   |  ___\____|_||_|_| |_|\____|\_/\_/
   | |

For further information check:

mount: mounting /dev/mmcblk0p1 on /mnt/sd/ failed: Invalid argument
init: Booting to single user mode

BusyBox v1.17.4 (2010-12-15 21:47:21 PST) hush - the humble shell
Enter 'help' for a list of built-in commands.

/ # ps aux
    1 root      1748 S    /init
    2 root         0 SW   [kthreadd]
    3 root         0 SW   [ksoftirqd/0]
    4 root         0 SW   [events/0]
    5 root         0 SW   [khelper]
    8 root         0 SW   [async/mgr]
   47 root         0 SW   [sync_supers]
   49 root         0 SW   [bdi-default]
   51 root         0 SW   [kblockd/0]
   57 root         0 SW   [kmmcd]
   72 root         0 SW   [rpciod/0]
   77 root         0 SW   [kswapd0]
   78 root         0 SW   [aio/0]
   79 root         0 SW   [nfsiod]
  603 root         0 SW   [spi_altera.2]
  625 root         0 SW   [mmcqd]
  641 root      2048 S    httpd -h /etc/html
  642 root      1740 S    inetd
  648 root      4004 S    /bin/sshd -f /etc/default/sshd_config
  653 root      2052 S    /bin/sh
  654 root      2052 R    ps aux

Now there is a (uC)Linux-system running in the FPGA ! If an Ethernet cable is connected a simple web-site can be visited at the boards IP address.